Field of the Invention
The present invention relates to current mirror type level converters and, more particularly, to current mirror type level converters utilizing MOS (Metal Oxide Semiconductor) transistors and performing a logic operation on input signals supplied thereto.
In recent years, Bi-CMOS circuits combining the respective characteristics of a bipolar transistor circuit and a CMOS (Complementary MOS) transistor circuit have been widely employed in integrated circuits. Integrated circuits employing Bi-CMOS circuits can operate at a high speed and with low power consumption by combining a bipolar transistor ECL (emitter coupled logic) circuit having high speed operation and a CMOS transistor circuit having low power consumption operation. A typical example is a memory circuit which uses CMOS transistors for memory cells and/or peripheral circuits thereof and an ECL circuit for interfacing with an external circuit.
However, since an ECL circuit and a CMOS circuit have different logic levels, a level converter is required therebetween to couple these circuits.
As an example of such level converters a current mirror type level converter is disclosed in Japanese Laid-Open Patent Application No. 62-154917. However, this converter requires true and complementary logic levels of input signal(s) for switching the mirror current, and hence the circuit construction becomes complicated and there is unavoidable signal propagation delay. These drawbacks become more conspicuous when a logic operation on two or more input signals is added to the level converter and/or when the number of logic stages is increased.